%Modeling

\begin{table*}[t]
\centering
    \begin{tabular}{|c|c||c|c||c|c|}
    \hline
    \multicolumn{2}{|c||}{CPU Parameters } & \multicolumn{2}{c||}{DRAM Cache} & \multicolumn{2}{c|}{Off-Chip DRAM} \\ \hline
    \# of Cores/ISA  & 4/ALPHA      		   & Frequency         & 1 GHz (2GHz DDR3)  & Frequency         & 800MHz(1.6 GHz DDR3)  \\ \hline
	CPU Type        & Out-of-Order         & Bus Width         & 128 bits           & Bus Width         & 64 bits               \\ \hline
    Frequency 		& 2 GHz		           &  Channels     	   & 1                  & Channels          & 1                     \\ \hline
    \multicolumn{2}{|c||}{SRAM Caches} 	   & Ranks per Channel & 2                  & Ranks per Channel & 2                     \\ \hline
    L1D\$ and L1I\$ & 2MB, 16 ways         & Banks per Rank    & 8                  & Banks per Rank    & 8                     \\ \hline
    L2 Shared \$    & 2MB, 16 ways         & Bytes per Row     & 2KB                & Bytes per Row     & 2KB                   \\ \hline
    Protocol        & MESI                 & Total Size        & 128MB              & Total Size        & 4GB                   \\ \hline          
    \end{tabular}
\end{table*}



